In a world where technological progress relentlessly rushes forward, one material stands out as key for the next generation of high-performance electronics – gallium nitride (GaN). This advanced semiconductor promises to revolutionize high-speed communication systems, power electronics, and the data centers of the future. However, despite its superior properties, the high cost of production and the complexity of integration with existing silicon technology have so far significantly limited its commercial application. But it seems this obstacle has now been overcome thanks to a revolutionary breakthrough by scientists at the Massachusetts Institute of Technology (MIT) and their collaborators.

They have developed an innovative, low-cost, and scalable manufacturing process that allows for the seamless integration of high-performance gallium nitride transistors directly onto standard silicon CMOS chips. This hybrid technology combines the best of both worlds: the proven, ubiquitous, and affordable silicon platform with the outstanding speed and efficiency of gallium nitride. The potential applications are vast, from significantly extending battery life and improving call quality on smartphones, to enabling new technologies and even the development of quantum computers.

A revolution in manufacturing: Joining the unjoinable

Previous methods of integrating gallium nitride and silicon were fraught with compromises. One approach involved soldering GaN transistors onto a CMOS chip, which limited their minimum size and, consequently, their maximum operating frequency. The smaller the transistor, the faster it can operate. Another, extremely expensive approach, involved placing an entire gallium nitride wafer on a silicon wafer. This resulted in a huge waste of expensive GaN material, given that its functionality is only needed in a few tiny transistors on the entire chip.

The new process, devised by the researchers, elegantly solves both problems. Instead of using a whole GaN wafer, they first produce a densely packed array of miniature transistors on its surface. Then, using extremely precise laser technology, they cut out each individual transistor, creating what they call a "dielet" – a tiny die measuring just 240 by 410 micrometers. These microscopic GaN "islands" are then selectively transferred and bonded only to the places on the silicon chip where they are truly needed. This approach drastically reduces costs because it uses the minimal, strictly necessary amount of gallium nitride, while the chip gains a significant performance boost.

Besides cost reduction, this method brings another key advantage: improved thermal management. By separating the GaN circuitry into discrete, small transistors that can be distributed across the surface of the silicon chip, heat concentration in one spot is avoided, which reduces the overall operating temperature of the system and increases its reliability and longevity.

Copper as the key to success: Cooler, cheaper, and more efficient

The core of the new integration process lies in an innovative bonding technique that uses copper. Each GaN transistor is equipped with tiny copper pillars on top, which directly bond to corresponding copper pillars on the surface of the silicon CMOS chip. This copper-to-copper bond can be achieved at temperatures below 400 degrees Celsius. This is a low enough temperature to avoid any damage to the sensitive structures of the silicon chip or the GaN transistor itself, preserving their full functionality.

This is a significant departure from existing techniques that often rely on gold for bonding. Gold is not only a considerably more expensive material, but it also requires much higher temperatures and greater forces to achieve a reliable bond. Additionally, gold can contaminate the tools used in most standard semiconductor foundries, which is why its use requires specialized and expensive facilities. "We were looking for a process that is cheap, low-temperature, and requires low force, and copper beats gold in all these categories. At the same time, it also offers better electrical conductivity," explains Pradyot Yadav, the lead author of the research.

What does this mean for the future of technology?

To demonstrate the practical applicability of their method, the research team fabricated a power amplifier, a key component in wireless communication devices like mobile phones. The results were impressive. Their hybrid chips, with a surface area of less than half a square millimeter, achieved significantly higher bandwidth and better signal amplification compared to devices that rely solely on silicon transistors. In a smartphone, this would directly translate to better call quality, higher wireless data transfer speeds, a more stable connection, and, most importantly to many, longer battery life.

Since the entire process can be integrated into standard semiconductor manufacturing procedures, this technology has the potential to improve not only existing electronics but also to open the door to completely new applications. For example, in data centers, which consume vast amounts of electrical energy, more energy-efficient chips could bring millions in savings and reduce the environmental footprint. In electric vehicles, they could enable smaller, lighter, and more efficient power management systems. In the long term, this integration scheme could even be key for quantum applications, as gallium nitride shows better performance than silicon at the cryogenic temperatures necessary for the operation of many types of quantum computers.

New tools for a new era

To bring this complex process to fruition, the team also had to create a specialized new tool. This device uses a vacuum to precisely pick up and position the tiny GaN "dielet" above the silicon chip, targeting the copper bonding interface with nanometer precision. Advanced microscopy is used to monitor the process in real-time. Once the transistor is perfectly aligned, the tool applies heat and pressure to create a strong and reliable bond.

"For every step in the process, I had to find a new collaborator who knew how to perform the technique I needed, learn from them, and then integrate it into my platform. It was two years of constant learning," points out Yadav, emphasizing the interdisciplinary nature of this breakthrough. The project's success is the result of collaboration with experts from Georgia Tech and the US Air Force Research Laboratory, utilizing advanced facilities at MIT.nano.

Confirmation from the industry and a look ahead

The significance of this achievement has been recognized outside of academic circles as well. Atom Watanabe, a scientist from IBM who was not involved in the research, commented: "To address the slowdown of Moore's Law in transistor scaling, heterogeneous integration has emerged as a promising solution for continuous system scaling, form-factor reduction, improved power efficiency, and cost optimization. This work represents a significant advancement by demonstrating the 3D integration of multiple GaN chips with silicon CMOS and pushes the boundaries of current technological capabilities."

By combining the best properties of silicon with the superior capabilities of gallium nitride, these hybrid chips could truly revolutionize numerous commercial markets. They represent a logical step in the evolution of semiconductors, offering a path toward faster, smaller, and more energy-efficient electronics that will power our technological future, from 6G networks to advanced artificial intelligence and space exploration.

Source: Massachusetts Institute of Technology