AI-based computing is entering a phase where energy efficiency can no longer be treated as a side issue. Training and running generative artificial intelligence, deep learning, and computer vision models are pushing the electricity consumption of data centers toward levels comparable to the consumption of entire countries. Estimates show that data centers consumed about 415 terawatt-hours of electricity in 2024, and by the end of the decade, that figure could more than double. In this context, every watt saved at the chip level becomes strategically important.

A group of researchers from the Massachusetts Institute of Technology (MIT) has therefore developed a new platform for electronics integration that attempts to solve the problem where it originates – in the chip architecture itself. Instead of keeping logic components and memory separate, as in classic circuits, they stack them vertically into a compact, three-dimensional "stack" built on top of an existing circuit. The new approach allows transistors and memory elements to be placed on top of one another in the back end of the chip, thereby drastically shortening the path data travels and reducing energy losses.

The key to this technology is a combination of a new material – amorphous indium oxide – and a carefully optimized manufacturing process that works at significantly lower temperatures than classic CMOS technology. This opens the possibility of upgrading already finished silicon circuits with additional "floors" of logic and memory, without destroying transistors made in the front end of the line. The result is an electronic platform that promises faster computing, lower energy consumption, and higher integration density, particularly attractive for applications like generative AI, deep learning, and real-time image processing.

The bottleneck of classic architecture: separated logic and memory

Most of today's computing systems still rely on an architecture that places logic (the processor) and memory in physically separate blocks. Logic transistors execute instructions, while memory elements – whether SRAM, DRAM, or flash – serve to store data and model parameters. Every time the processor needs data, it must "travel" through a network of wires, interconnects, and buses. This constant traffic of information between logic and memory is known as the von Neumann bottleneck and is today one of the main sources of inefficiency.

As models become larger and the amount of data grows exponentially, the energy cost of moving bits itself becomes greater than the cost of computing. Analyses show that a significant part of the energy in data centers goes precisely to data transfer within the chip, between chips, and to and from external memory. Additionally, every extra hop between levels of the memory hierarchy introduces latency and limits the total speed of the system. Therefore, an increasing part of research is directed toward the concept of "in-memory" computing and toward three-dimensional integration that shortens the data path.

Standard CMOS chips are strictly divided into the front-end-of-line and back-end-of-line processes. In the front end (front-end-of-line), active components like transistors and capacitors are made, while the back end (back-end-of-line) serves to route wires, interconnects, and metallization that connect these components into functional circuits. Although the back-end process has seen significant improvements over the years, it still serves primarily as a "highway for electrons," rather than an active zone where calculation takes place.

The problem arises when we want to build additional active layers above the already formed transistors in the front end. Classic silicon transistors require high processing temperatures, often hundreds of degrees Celsius, which would irreversibly damage or destroy the devices located underneath. Because of this, vertical stacking of logic and memory within the same chip, with a density suitable for modern AI accelerators, has so far remained largely in the domain of theory and simulations.

New strategy: active components in the back end of the chip

The MIT team decided to "flip" the usual approach and use the back end of the process as a space for embedding additional active layers. Instead of trying to bake silicon again at high temperatures, the researchers developed transistors that can be made at temperatures around 150 degrees Celsius, directly onto the back-end structures. Thus, an additional layer of logic and memory is created that sits above the existing CMOS circuit but does not damage it.

The basic idea is that on an already finished chip, where classic silicon transistors are still responsible for part of the work, new layers of transistors and memory are added in the back end. These layers take over the most energy-intensive tasks – for example, local data processing and storage of neural network parameters – while the basic logic in the front end is used as the "anchor" of the entire system. The result is a hybrid architecture in which different materials and technologies complement each other.

For such an approach to succeed, it is necessary to find materials that retain good electronic characteristics even at very small dimensions, but can simultaneously be deposited at low temperatures. This is exactly where amorphous indium oxide comes onto the scene, a material that has attracted great attention in recent years as a candidate for transistors in the back-end-of-line process and in monolithic 3D integration.

Amorphous indium oxide: a channel two nanometers thick

Amorphous indium oxide belongs to the group of amorphous oxide semiconductors, materials that offer a combination of high charge mobility, good scalability, and the ability to be deposited in thin layers at relatively low temperatures. In the MIT paper, this material takes on the role of the active channel of transistors made in the back end of the chip. The channel is the layer where the key function of the transistor takes place – the controlled switching on and off of the flow of electrons between the source and the drain.

The researchers managed to form a layer of amorphous indium oxide about two nanometers thick, which is roughly a dozen atomic layers. In this regime of ultra-thin films, every defect in the material network has a relatively large impact on the behavior of the device. Particularly important are so-called oxygen vacancies – places in the network where an oxygen atom is missing – because precisely these defects can act as donor sites that provide free electrons needed for conducting current.

For the correct operation of the transistor, it is necessary to find a balance: too few vacancies mean that the channel is too weak a conductor and the device is hard to turn on, while too many defects lead to current leakage, instability, and increased energy consumption in the off state. The MIT team therefore devoted a large part of the work to precise control of the deposition process and subsequent processing of amorphous indium oxide, so that the number and distribution of defects would be exactly as needed for stable operation at nanometer scales.

The result is an extremely small transistor with a channel layer of only a few nanometers, which can reliably switch between on and off states with very little additional energy. According to the researchers, such optimized transistors achieve performance comparable to, and even better than, currently the most advanced solutions in their class, with lower energy consumption per operation.

Memory integrated into the transistor: ferroelectric hafnium-zirconium oxide

Based on the same approach, the researchers also made transistors with built-in memory, also in the back end of the chip. These so-called memory transistors have dimensions of the order of magnitude of 20 nanometers, and use ferroelectric hafnium-zirconium oxide as the key memory layer. It is a material that can retain two stable states of electric polarization, making it suitable for low-energy, non-volatile memories.

Ferroelectric hafnium-zirconium oxide (HfZrO or HZO) has become one of the stars of research in the field of next-generation memories in the last ten years. Unlike older ferroelectric materials, this compound is compatible with the standard CMOS process and can be crystallized at temperatures that are low enough not to damage existing structures in the back-end-of-line process. Because of this, HZO is increasingly mentioned as a candidate for integrating ferroelectric memories directly onto logical chips.

In the MIT demonstration, a ferroelectric layer of hafnium-zirconium oxide was added above the channel of amorphous indium oxide, thereby creating a compact memory transistor. By changing the polarization of the ferroelectric layer, the effective threshold for turning on the transistor changes, which allows the storage of logical states without the need for constant refreshing. Such an approach combines the functions of logic and memory in the same physical element, so the same transistor can be used for both data processing and their storage.

These memory transistors show extremely fast state switching, of the order of magnitude of ten nanoseconds, which is so fast that it approaches the limits of the measuring instruments used in the experiment. Even more importantly, this change of state is achieved at significantly lower voltages than with similar devices, which further reduces overall energy consumption.

Energy gain: less data movement, more computing per joule

Merging logic and memory in a vertically stacked structure dramatically affects the energy profile of the system. When a transistor can locally store data it is currently processing, there is no need for bits to be constantly sent through the chip and to external memory. Every eliminated hop through the memory hierarchy means fewer losses in wires and interconnects, less heating, and less energy spent on cooling.

For AI accelerators, in which the same model parameters and the same blocks of data are read and written billions of times during operation, this difference can be decisive. Estimates by global organizations show that the electricity consumption of data centers could rise to about 950 terawatt-hours annually by 2030, primarily due to the growth of AI workloads. Even a relatively small percentage of savings per chip, at the level of a few tens of percent less consumption per operation, can turn into significant savings at the level of entire data centers and energy systems.

MIT's approach therefore fits into a broader strategy of "efficient AI," which counts not only on renewable energy sources and better infrastructure but also on significantly more efficient computing in the silicon base itself. By vertically stacking transistors and memory, it is possible to achieve more operations per joule of energy, without necessarily increasing the clock speed or adding an ever-increasing number of conventional cores.

Connecting with global trends in the semiconductor industry

The work of the MIT team builds upon a strong research wave that has in recent years been looking for ways to use amorphous oxide semiconductors and ferroelectric materials in the back end of the process for monolithic 3D integration. Numerous academic groups and industrial laboratories have already shown that indium oxide and related materials can be deposited in ultra-thin layers, with high charge carrier mobility and stable operation at low consumption.

In parallel, ferroelectric memories based on hafnium oxide and hafnium-zirconium oxide are being intensively researched. They offer non-volatile data storage, the possibility of operation at low voltages, and compatibility with existing silicon technologies. The latest reviews from literature show that ferroelectric transistors can achieve switching times of the order of a few nanoseconds, operation with voltage levels below five volts, and endurance of billions of cycles, making them serious candidates for future embedded memories and in-memory computing.

MIT's demonstration combines these trends into one system: it uses amorphous indium oxide to build low-temperature transistors in the back end of the chip and hafnium-zirconium oxide for the implementation of compact ferroelectric memory. Additionally, the researchers, in collaboration with partners, have also developed performance models of these transistors, which is a key step toward embedding such elements into larger circuits, such as accelerators for neural networks or specialized processors for computer vision.

From research prototype to industrial application

The new transistors and memory elements were presented at the prestigious IEEE International Electron Devices Meeting (IEDM), which is considered one of the main places where the industry and the academic community exchange results on the future of semiconductor technology. The fact that researchers from MIT, the University of Waterloo, and the industrial giant Samsung Electronics participated in the work shows that the idea of vertically stacking logic and memory in the back end of the chip is already being very seriously considered outside the laboratory as well.

The path from a research prototype to a commercial product is nevertheless long. It is necessary to prove the reliability of the device over billions of cycles, show that new materials can be reproducibly manufactured in large batches, and integrate design tools that will allow engineers to use these transistors and memories in real projects. Performance modeling, which MIT and partners are working on, is one of the first steps: it allows circuits that would use such elements to be simulated today and their benefit compared to classic architectures to be estimated.

The semiconductor industry is simultaneously exploring other approaches to three-dimensional stacking – from advanced memory technologies to logic transistors that are stacked on top of each other in complementary structures. However, solutions that can be integrated into existing CMOS processes, without drastic changes in production plants, have the greatest chances for rapid adoption. In this sense, amorphous oxide semiconductors and hafnium-zirconium oxide have an important advantage because they already fit into the existing infrastructure.

Next steps: scaling, optimization, and new functionalities

The research team from MIT has already announced that the next steps include further improvement of the performance of transistors made in the back end, as well as finer control of the properties of ferroelectric hafnium-zirconium oxide. The goal is to simultaneously increase operating speed, reduce required voltages, and maintain stability during long-term operation. In doing so, understanding the fundamental physics at the level of individual ferroelectric domains in nanometer structures will also play an important role.

It is particularly interesting that these miniature memory transistors serve not only as functional elements but also as an experimental platform for studying the physics of ferroelectrics in extremely scaled dimensions. By observing how domains behave in structures the size of only a few tens of nanometers, researchers can test theoretical models and devise new ways to utilize ferroelectricity in computing, sensors, or neuromorphic circuits.

In a broader sense, the work of the MIT team is part of a global race for new materials and architectures that could replace or upgrade silicon when we approach the physical limits of its scaling. The combination of three-dimensional integration, new semiconductors, and ferroelectric memories offers a path toward chips that simultaneously provide greater processing power, lower energy consumption, and more flexible data organization – exactly what is needed so that generative artificial intelligence and other data-intensive tools can develop without causing an energy crisis.

Although time will pass before such transistors and memories come to life in mass products, the direction is clear: future generations of computing systems will increasingly resemble layered structures in which data is processed where it is created, and the boundary between logic and memory gradually disappears. In that scenario, solutions like MIT's platform for stacking transistors and memory in the back end of the chip can play an important role in maintaining the growth of computing power, while simultaneously keeping energy consumption under control.